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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:50:16 12/02/2009 
-- Design Name: 
-- Module Name:    InstructionRegister - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity InstructionRegister is
    Port ( instruction : in  STD_LOGIC_VECTOR (31 downto 0);
			  clk : in  STD_LOGIC;
           OP : out  STD_LOGIC_VECTOR (5 downto 0);
           rs : out  STD_LOGIC_VECTOR (4 downto 0);
           rt : out  STD_LOGIC_VECTOR (4 downto 0);
           rd : out  STD_LOGIC_VECTOR (4 downto 0);
           shift : out  STD_LOGIC_VECTOR (4 downto 0);
           funct : out  STD_LOGIC_VECTOR (5 downto 0));
end InstructionRegister;


architecture asigne of InstructionRegister is

		signal s_instr : STD_LOGIC_VECTOR (31 downto 0);

begin
		process(clk)
		begin
			if clk'event and clk='1' then
				s_instr <= instruction;
			end if;
		end process;
		
		OP <= s_instr(31 downto 26);
		rs <= s_instr(25 downto 21);
		rt <= s_instr(20 downto 16);
		rd <= s_instr(15 downto 11);
		shift <= s_instr(10 downto 6);
		funct <= s_instr(5 downto 0);
end asigne;


library IEEE;
use IEEE.std_logic_1164.all;

package mips_IR is
	component InstructionRegister
		Port ( instruction : in  STD_LOGIC_VECTOR (31 downto 0);
				clk : in  STD_LOGIC;
				OP : out  STD_LOGIC_VECTOR (5 downto 0);
				rs : out  STD_LOGIC_VECTOR (4 downto 0);
				rt : out  STD_LOGIC_VECTOR (4 downto 0);
				rd : out  STD_LOGIC_VECTOR (4 downto 0);
				shift : out  STD_LOGIC_VECTOR (4 downto 0);
				funct : out  STD_LOGIC_VECTOR (5 downto 0));
	end component;
end mips_IR;